Running minimum message passing ldpc decoding

ABSTRACT

The invention relates to a decoding method for decoding Low-Density Parity Check codes in transmission and recording systems. The method comprises a running minimum loop comprising the following iterative sub-steps:—reading a reliability value from the input sequence of input reliability values,—comparing said reliability value with a stored value,—overwriting the stored value with said reliability value if said reliability value is smaller than said stored value.

FIELD OF THE INVENTION

The invention relates to a decoding method for delivering soft-decisionoutputs from codeword symbols encoded with a Low-Density Parity Check(LDPC) code.

The invention applies to digital transmission and recording systems,such as in magnetic recording, optical recording, telecommunications(e.g mobile and optical networks), in-house radio-networks and systemsthat involve space-time coding, etc. It is particularly advantageous fortwo-dimensional optical storage, which is one of the potentialtechnologies for the next generations of optical storage.

BACKGROUND ART

The article: “Reduced Complexity Iterative Decoding of Low-DensityParity Check Codes Based on Belief Propagation” by Marc P. C. Fossorierpublished in IEEE Transactions on Communications, vol. 47, No. 5, May1999, [1] describes an iterative algorithm for decoding LDPC codes. LDPCcodes are error-correcting codes of which the decoders can accept softdecision inputs. LDPC decoding does not involve Viterbi-kind ofalgorithms and is much less complex. LDPC codes were invented in the1960s by Gallager. Later in the 1990s, Berrou et al. invented Turbocodes. Then, MacKay and others discovered that Turbo codes were similarto LDPC codes.

In the sequel, the abbreviation LDPC will be used to designate all codeswith a Low-Density Parity Check matrix, including Turbo codes.

SUMMARY OF THE INVENTION

It is an object of the invention to provide a decoding method for LDPCcodes that enables to save a significant amount of memory space indecoders.

In accordance with the invention, a decoding method for LDPC codes asmentioned in the opening paragraph is provided. Said LDPC codes aredefined by a number of codeword symbols being checked by a number ofparity check equations, each parity check equation being destined tocheck a limited number of codeword symbols and each codeword symbolbeing destined to be checked by a limited number of parity checkequations. In accordance with the invention, the method comprises astep, denoted running minimum loop, of determining a minimum value froman input sequence of input reliability values associated to a set ofcodeword symbols checked by a same parity check equation, said runningminimum loop comprising the following iterative sub-steps:

reading a reliability value from the input sequence of input reliabilityvalues,

comparing said reliability value with a stored value,

overwriting the stored value with said reliability value if saidreliability value is smaller than said stored value.

Using such running minimum step for determining a minimum value from aninput sequence of a plurality of input reliability values avoids storingthe results of all comparisons. This is in practice more feasible on asingle chip than storing all the comparison results.

In accordance with a particular embodiment of the invention, the methodcomprises a step of computing, for each parity check equation, an outputsequence of output reliabilities from said input sequence of inputreliabilities, each output reliability of the output sequence beingequal to the minimum value of all input reliabilities except the onewith the same index in the input sequence, said minimum value beingdetermined with said running minimum step. In this particular case, allresults in the output sequence, except the one having the index of theoverall minimum value, are equal to the overall minimum value, theresult having the index of the overall minimum value being equal to thesecond-to-minimum value. As a consequence, only three values need to bestored, that are the overall minimum value, the overallsecond-to-minimum value and the index of the overall minimum value inthe input sequence.

In accordance with a preferred embodiment of the invention, the inputsequence of input reliability values is produced from said codewordsymbols received from a transmission channel or a recording channel. Theinput reliability values are derived from the absolute values of LogLikelihood Ratios (LLR) of the codeword symbols. In general, the LLR ofa binary random variable X is defined as:LLR _(X)=log(Pr{X=0}}/Pr {X=1}),where Pr{X=0} is the probability that X=0. Using Log Likelihood Ratiosrepresentations of probabilities enables the decoding algorithm tobehave linearly in the input log-likelihoods that are received over thechannel. This makes the decoding result less prone to degradation byerrors in the knowledge of the signal to noise ratio.

The invention also relates to:

a receiver for receiving from a channel medium codeword symbols encodedwith a Low-Density Parity Check code,

an optical storage medium for use in such a receiver,

a system comprising a source for delivering codeword symbols encodedwith a Low-Density Parity Check code through a channel medium and areceiver for receiving said codeword symbols from the channel medium,

a computer program product for carrying out the decoding method,

a signal for carrying the computer program and

making available for downloading the computer program.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention and additional features, which may be optionally used toimplement the invention, are apparent from and will be elucidated withreference to the drawings described hereinafter and wherein:

FIG. 1 is a conceptual diagram for illustrating an example of a methodof decoding LDPC codes in accordance with a first embodiment of theinvention,

FIG. 2 is a conceptual diagram for illustrating an example of a methodof decoding LDPC codes in accordance with a first embodiment of theinvention,

FIG. 3 is a schematic block diagram for illustrating an example of asystem comprising a receiver in accordance with the invention.

DETAILED DESCRIPTION OF THE DRAWINGS

The following remarks relate to reference signs. Same block labels inall figures usually indicate same functional entities.

Before describing the core of the invention, a definition of LPDC codesto which the invention applies is given herein after. LDPC codes aresparse matrix error-correcting codes for use e.g. in digitaltransmission and recording systems. They proved to be very efficient inenabling the decoder to retrieve the original information delivered bythe source. The parity check matrix H of an error-correcting code is abinary matrix such that Hc=0, if and only if c is a codeword. That is,the code space is the null space of matrix H. The “low density” propertyof the parity check matrices refers to the fact that if the block length(i.e. codeword length) of these codes goes to infinity, the number of1's per row K and the number of 1's per column J≧3 remain finite. Therate of an LDPC code equals R=1−J/K.

Gallager's construction method described in R. G. Gallager, “Low densityparity check codes,” IRE Transactions on Information Theory IT-8, pp.21-28, 1962 [2] was used to create a parity check matrix H that hasexactly J ones per column and exactly K ones per row. To date, moregeneral constructions of LDPC codes are known. In these generalized LDPCcodes the number of ones per row and per column may vary according to acertain probability distribution. The invention applies to both types ofcodes, as well as to Turbo codes, which have similar properties.

These codes are decoded using a so-called message-passing algorithm.When making an LDPC decoder chip, a disadvantage of the classicalsum-product message-passing algorithm is that it involves quite a numberof multiplications. To circumvent this complexity, a trick can beapplied that is well known in the area of Turbo coding, called“approximation of the Box-function with the minimum reliability input”.The Box function consists in replacing the reliability of the exclusiveOR of two entities by a function of the reliabilities of both entities.Its approximation (letting aside the sign) consists in replacing theso-called Box function with the minimum of the absolute values of thereliabilities. The same approximation is used for the message-passingalgorithm in accordance with the invention, wherein it turns out to haveeven more far-reaching positive consequences.

FIG. 1 is a bi-partite LDPC graph, which is a graphical representationof the parity check matrix, for illustrating the so-calledmessage-passing algorithm in accordance with the invention. Thebipartite graph comprises two kinds of nodes at either sides of thegraph. One kind of nodes on the left side is the codeword symbol nodes.They represent the input codeword symbols. The other kind of nodes onthe right side is the parity check nodes. They represent the paritycheck equations. If a certain parity check equations parity checks Kcodeword symbols, these K codeword symbol nodes are linked with thepertaining parity check node in the graph. Thus, the degree of theparity check nodes (the number of edges connected) equals K. The degreeof a codeword symbol node equals J because the number of 1's in a columnof the parity check matrix H equals J.

For example, the length of an LDPC code such that its performance getsclose to the Shannon capacity limit is e.g. ca. 10000 bits. For theintended application area of optical storage, a high rate code, e.g.rate 0,90 is required (it is to be noted that for low rate codes, e.g.rate 0,5 the invention is also advantageous). That means that there are(1−0.90)*10000=1000 parity check equations. The 10000 codeword symbolsare represented by as many nodes on the left side of the bipartitegraph. The 1000 parity check equations are represented by as many nodeson the right side of the graph. In between the left nodes and the rightnodes edges are laid out. E.g. each left node is the end point of 3edges (J=3), each right node is the end point of 30 edges (K=30) so thatthere are 3×10,000=30×1000 edges. This means that the sum of the 30codeword symbols whose nodes are connected to a parity check node mustadd up (modulo 2) to zero; i.e. have predetermined parity. Each codewordsymbol is incorporated in 3 check equations. More precisely, thecodeword length (ca. 10000 in the example) should be a multiple of K,for Gallager codes.

Decoding on such a bipartite graph is done with the message-passingalgorithm. The original LDPC message-passing algorithm is called thesum-product algorithm and is described in F. R. Kschischang, B. J. Frey,H. A. Loeliger, “Factor Graphs and the Sum-Product Algorithm,” IEEETrans. on Information Theory, Volume IT-47, No. 2, February 2001 [3].The sum-minimum algorithm is a simplified multiplication-free variant ofthe sum-product algorithm. A standard implementation of either thesum-product or the sum-minimum algorithm goes as follows. Messagescarrying probability information flow over the edges of the graph,alternatively, from the codeword nodes to the parity check nodes, andback.

In a typical implementation, e.g. all most recent outgoing messages (orall incoming messages, or both) are stored in the nodes. In the leftnodes this leads to a storage requirement of at least 3 messages, ofapproximately one byte size each, for each of the 10 000 nodes. For theright nodes this leads to a storage requirement of at least 30 messagesfor each of the 1000 nodes. In total two times 30,000 messages are to bestored.

Before describing the algorithmic structure of LDPC decoding, thetransformation from sum-product structure to a sum-minimum structure isexplained herein after. This kind of transformation is used in manyerror corrector implementations, such as Viterbi and Turbo decoders. Itusually makes use of log-likelihood ratio (LLR) representations ofprobabilities, but another representation could be used. In general, theLLR of a binary random variable X is defined as:LLRX=log(Pr{X=0}}/Pr{X=1}),where Pr{X=0} is the probability that X=0.

If no information about X is available, and both values 0 and 1 areequally likely, then LLR_(X)=0. Generally, the more LLR_(X) informationabout X is available, the more the absolute value of the LLR_(X) willdeviate from zero. To derive a hard decision value for X from theLLR_(X), one only needs to consider the sign of LLR. If LLR_(X)>0, thevalue X=0 is more likely. If LLR_(X)<0, the value X=1 is more likely.Therefore, the operations that will be performed in the simplifieddecoding algorithm, that is, the sum-minimum algorithm, are:

-   -   summation of log-likelihoods (in the codeword symbol nodes),    -   minimization of absolute values of log-likelihoods, with        multiplication of the signs ±1 in the parity check nodes (the        multiplication of the ±1 signs corresponds to taking the        exclusive OR of the pertaining hard decision bits 0/1).

The decoding algorithm in accordance with a preferred embodiment of theinvention uses such log-likelihood ratio representations ofprobabilities. It will thus behave linearly in the input log-likelihoodsthat are received over the channel. Actually, these log-likelihoods canbe produced by a bit-detector, also called equalizer. If we multiply theinput log-likelihoods of the decoding algorithm with a constant alpha,then all log-likelihoods no matter after how much iteration also scaleup with the same alpha. Thus, this alpha has no influence on the signsof the log-likelihoods, and therefore also has no influence on harddecision values of codeword bits after all iterations are done. Such ascaling with an unknown alpha occurs, when the input log-likelihoods arenormalized with the correct or incorrect signal to noise ratio of thechannel. The sum-product algorithm would convert log-likelihood ratiosback to probabilities, in some form, and thus be sensitive to errors inthe estimate of the signal to noise ratio. Thus, the fact that thesignal to noise ratio does not need to be known in our decodingalgorithm, makes the decoding result less prone to degradation by errorsin the knowledge of the signal to noise ratio. In addition, as will beexplained further later, also the memory architecture will be greatlyinfluenced, in a positive manner, by the use of a sum-minimum instead ofa sum-product decoding algorithm.

In the bipartite graph of FIG. 1, different operations are used insidethe codeword symbol nodes and the parity check nodes. In the codewordsymbol nodes, the combined LLR of multiple independent (the assumedindependence is an approximation, which holds only at the start ofdecoding a codeword, and becomes increasingly invalid) sources ofinformation about the random variable equals the sum of the individualLLRs. In the parity check nodes, the LLR of an exclusive OR of multipleindependent (again, the independence is only an approximation) binaryrandom variables is a so-called Box function of the input LLRs. Theso-called Box function is described for example in [3] and in J.Hagenauer, E. Offer, L. Papke, “Iterative decoding of binary block andconvolutional codes Information Theory,” IEEE Transaction on InformationTheory, Volume 42 Number 2, pages 429-445, March 1996 [4]. A principlethat the codeword symbol nodes and the parity check nodes have in commonis that soft information that flows into a node over a certain edge, maycertainly not contribute to the soft information that flows out of thatnode over the same edge.

The following is a pseudo code text of the sum-product algorithm. Thealgorithm works with LLRs, which alternatively flow from all codewordbit nodes over all edges to all parity check nodes, and back. To startthe algorithm up, we assume that all zeroes LLR's have been sent by theparity check nodes and received by the codeword symbol nodes. Note, thatfor each codeword symbol node the corresponding channel LLR also is anincoming edge to that node. “FOR 45 ITERATIONS DO” “FOR ALL CODEWORD BITNODES DO” “FOR EACH INCOMING EDGE A” “SUM ALL INCOMING LLRs EXCEPT OVERA” “SEND THE RESULT BACK OVER A” “NEXT EDGE” “NEXT CODEWORD BIT NODE”“FOR ALL PARITY CHECK NODES DO” “FOR EACH INCOMING EDGE” “TAKE THE BOXFUNCTION OF ALL INCOMING LLRs EXCEPT OVER A” “SEND THE RESULT BACK OVERA” “NEXT EDGE” “NEXT PARITY CHECK NODE” “NEXT ITERATION”

The soft output codeword symbols of the algorithm are equal to the sumof all incoming LLRs (channel LLR plus the edges coming in from theparity check nodes) in a codeword bit node. An initial investigation ofthe sum-product LDPC decoding algorithm shows that even after loadbalancing, an excessive amount of multiplications must be performed.Common sub-expression minimization can roughly halve this number, butthis is still not sufficient.

In the sum-product algorithm, one has the choice to do a large number oftable lookups of a certain so-called Box-function. Alternatively, onecan use a probability difference representation of the likelihoods inthe parity check nodes (see[3]) and do a large number of fixed pointmultiplications. A minimization operation is relatively cheap inhardware. On the other hand, carrying out multiplications or doing largenumber of fixed-point to fixed-point table lookups takes up much chiparea and is much slower.

With the sum-minimum algorithm, e.g. with NJ/K=1000 parity check nodes(N=10000, J=3) we need to take the minimum and second to minimum of K=30input terms per check node, for a total of up to e.g. 45 iterations perreceived codeword. This has turned out to be feasible on a single chip,which would not have been the case if we had had to do as manymultiplications. In the sum-minimum algorithm, one parity check nodeoperation amounts to the following. For each of the k=0, 1, . . . , K−1parity check nodes with which it is connected:

-   -   compute the exclusive OR of all hard bits output by the        connected codeword symbol nodes (as determined by the signs of        the output log-likelihood ratios) except the k-th one,    -   compute the minimum of all K absolute values of the        log-likelihood ratios of the codeword bit nodes to which the        parity check node is connected except the k-th one.

A cheap way (in hardware) to compute the K exclusive OR results is tocompute the exclusive OR of all K input bits. Now, the exclusive OR ofall K input bits except one can be obtained by taking the exclusive ORof the aforementioned total and taking the exclusive OR with the inputbit that is to be let aside.

With respect to the K minima that have to be computed during a paritycheck node operation and in accordance with the principle mentionedabove that soft information that flows into a node over a certain edgeshall not contribute to the soft information that flows out of that nodeover the same edge, the invention takes into consideration thefollowing. Consider the k-th input to the parity check node, and assumethat its absolute value of the log-likelihood ratio is not the minimumof all K such inputs. Then, the minimum value of all K inputs except thek-th one, equals the overall minimum of the K values. In case, the k-thlog-likelihood ratio does have the absolute minimum value of all Kinputs, the minimum of the K inputs except the k-th one equals thesecond-to-minimum value.

As an example, suppose the 30 input reliabilities of a given right nodeat a given iteration are the input sequence of Table 1 below: TABLE 1input sequence of input reliabilities 10.2 6.0 2.3 20.7 18.2 8.9 14.21.8 12.2 19.4 7.5 30.0 28.8 5.9 2.9 5.7 8.2 15.8 17.0 13.1 10.6 18.7 9.212.0 20.8 15.6 13.9 11.4 16.7 20.1

The minima of all input reliabilities except one, where the first one isomitted, then the second one, then the third one, etcetera, results inthe output sequence of Table 2 below: TABLE 2 output sequence of outputreliabilities 1.8 1.8 1.8 1.8 1.8 1.8 1.8 2.3 1.8 1.8 1.8 1.8 1.8 1.81.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8

It is to be noted that the output sequence comprises only two differentvalues. One is the overall minimum value and corresponds to the outputresult in every position except one and the other is the overallsecond-to-minimum value which index corresponds to the position of theoverall minimum value in the input sequence. Thus, in a parity checknode, the sequence of minima of K values except the k-th one, k=0, 1, .. . , K−1 can be stored using only three numbers:

the overall minimum value,

the overall second-to-minimum value,

the index k for which the minimum input value occurs,

Taking advantage of the observations made above in order to save memoryspace in decoders, the message-passing algorithm in accordance with theinvention, can be summarized as follows. First, a minimum value shall bedetermined from an input sequence of input reliability values associatedto a set of codeword symbols checked by a same parity check equation.Then, the method performs a so-called running minimum loop comprisingthe following iterative sub-steps:

reading a reliability value from the input sequence of input reliabilityvalues,

comparing said reliability value with a stored value,

overwriting the stored value with said reliability value if saidreliability value is smaller than said stored value.

Using such so-called running minimum step avoids storing the results ofall comparisons corresponding to Table 2. Instead, a running minimum isupdated when the input reliabilities of the input sequence are read,which enables saving memory space. In practice, when starting therunning minimum step, the initially stored value could be a pre-storedreference value, whose value has been chosen appropriately, and that isupdated with values read from the input sequence. In subsequent loops,the stored value could be a reliability value, smaller than theinitially stored value, overwritten from the input sequence, which is tobe updated when the other reliability values are read from the inputsequence. Despite the fact that the running minimum step described aboverelates to the running overall minimum value of the input sequence ofreliabilities, a similar method can also be applied to determine bothoverall minimum and second-to-minimum values. In this case, the runningminimum step comprises the following iterative sub-steps:

reading a reliability value from the input sequence of input reliabilityvalues,

comparing said reliability value with a first and second stored value,

overwriting the first stored value with said reliability value if saidreliability value is smaller than said first and second stored value,

overwriting the second stored value with said reliability value if saidreliability value is smaller than said second stored value and biggerthan said first stored value.

It is to be noted that in the example described below with respect toFIG. 1, each input reliability value associated to a codeword symbol isderived from the parity checks operated on said codeword symbol.

In the particular case of a message-passing algorithm comprising a stepof computing, for each parity check equation, an output sequence ofoutput reliabilities from said input sequence of input reliabilities,each output reliability of the output sequence being equal to theminimum value of all input reliabilities except the one with the sameindex in the input sequence, the minimum value can be determined withsaid running minimum step. In this particular case, the invention maynormally lead to store only three values in each symbol node, that arethe overall minimum value, the overall second-to-minimum value and theindex of the overall minimum value in the input sequence, because allresults in the output sequence, except the one having the index of theoverall minimum value, are equal to the overall minimum value, theresult having the index of the overall minimum value being equal to thesecond-to-minimum value.

To implement the invention summarized hereinabove, the following remarksare made. The input sequence of input reliability values is normallyproduced from said codeword symbols received from a source. The sourcemay be e.g. a transmission channel or a recording channel. As alreadymentioned, the input reliability-values may be derived from the absolutevalues of Log Likelihood Ratios of the codeword symbols or from otherrepresentation of the probabilities of the codeword symbols. The sum ofall codeword symbols in the set, which are checked by a same paritycheck equation, has predetermined parity.

The behavior of the message-passing algorithm described above can beexplained using FIG. 1. Information (e.g. received messages, orinformation derived from received messages) is stored in all nodes.Alternately, messages flow across all edges from left to right (onehalf-iteration). Then, messages flow across all edges from right to left(second half-iteration). In this figure, the fact that information isstored in both the codeword bit nodes and the parity check nodes isindicated with two intersections (dashed lines) of the graph. Thecodeword bit nodes are on the left side. The parity check nodes are onthe right side. In reality, for a rate R=0.9, J=3 code, each codewordsymbol node has J=3 connected edges, each parity check node hasK=J/(1−R)=30 connected edges. The default way of message passing in anLDPC graph is to first use information stored in the codeword bit nodesto compute output messages that flow to the right of the graph. Then,use information (messages) stored in the parity check nodes to computemessages that all flow to the left side of the graph.

To take advantage of the invention enabling not storing all 30 valuesbut only the minimum, the second-to-minimum, and the index, the incomingmessages should be processed in a parity check node and the outputmessages that have been prepared should be stored. For this, as alreadymentioned, only three numbers per parity check node (and some bits) needto be stored. If the prepared output messages are also stored in thecodeword symbol nodes, J=3 numbers would have to be stored per codewordbit node. The fact that there are 1/(1−R)=10 times more codeword symbolnodes than parity check nodes, and that a similar amount of data foreach node are stored, makes evident that the storage requirements wouldbe dominated by the codeword symbol nodes.

FIG. 2 shows a bipartite graph in accordance with a preferred (moreoptimal) embodiment of the invention. In this embodiment, messageinformation regarding the left nodes and message information regardingthe right nodes are not stored to successively compute new right nodeinformation from the left node information and vice versa. Instead, theoutput message information of the parity check nodes are stored twice,one old (current) sequence of information, and one new sequence ofinformation, which is in the process of being computed (from the oldsequence). This time, the old output message information of the paritycheck nodes and a new sequence of the same information are stored. Thecomputations can then be summarized as follows:

starting from the “current” values in the right nodes connected to aleft node,

extracting the right node output messages from the minima, second tominima and the index and forward that information to a given left node(or a number of them),

performing the left node processing and

immediately going back and incorporating the left node output messagesthat come from that left node in the (J=3) right nodes' “new” values,where running minima and running second to minima are maintained.

In the not optimal embodiment previously described, the storagerequirement for the codeword symbol nodes was approximately 10 (=K/3)times larger than that of the parity check nodes. Now that all storagehave been moved to the right side of the graph (the parity check nodes),a reduction in the storage requirement of roughly a factor of 10 can beobtained.

The running minimum algorithm enabling to save memory space in both thesymbol nodes and the parity check nodes will now be described in moredetails with respect to the mentioned numerical example. For each of theca. 10000 codeword symbols, one soft channel output (LLR), an 8 bitfixed point, has to be stored, which gives a storage requirement of 80kbit. There are two sections in the parity check node memory: onesection for all input values of an iteration, one section for all outputvalues of an iteration. The input memory section and the output memorysection are interchanged after one iteration, so that the former outputnow becomes input data.

For each of the 1000 parity check nodes, we thus have two copies of:

M, which denotes the running minimum of absolute log-likelihood inputs(a fixed point),

MM, which denotes the running “second to minimum” absolutelog-likelihood inputs (a fixed point),

I, which denotes the index of which of K=30 absolute log-likelihoodinputs is minimal (an edge label),

T, which denotes 1 bit exclusive OR of all K=30 hard bit inputs,

S[30], which denotes the sign bits of the K=30 inputs to check nodes,which makes in total, approximately-1000×2×(8+8+5+1+30 bit)=100 kbit.The total RAM storage requirement per LDPC decoder is ca. 80 kbit+100kbit=180 kbit. Initially, in the input parity check node memory section,we replace all (M,MM,I,T,S) by (0,0, X,X,X[30]), where “X” denotes“don't care”. The following is a pseudo code text of the so-calledrunning minimum algorithm: “FOR 45 ITERATIONS DO ...” In the outputparity check node memory section, set : (M, MM, I, T, S) = (MAX, MAX, X,0, X[30]) where MAX denotes the maximum value in the fixed pointrepresentation used. “FOR ALL CODEWORD BIT NODES DO ...”Fetch the J=3 inputs of that codeword symbol node. Each of the J=3incoming branches, has a constant label (1 . . . 30=K), which representsthe how many-th edge it is in its parity check node. For each of the J=3incoming branches, if the I-field of the right node equals the constantlabel of the edge: fetch the second to minimum MM out of the inputparity check node memory word, otherwise fetch the minimum M. M and MMare nonnegative reliabilities (absolute values of LLR's). Give thefetched reliability a sign bit equal to:T+S[edge label]mod 2(this way get the exclusive OR of all 30 hard bits except one). Sum theJ=3 signed fetched numbers (these numbers are the input messages to thecodeword bit node) and add the channel input value stored for that leftnode. From this total, for each of the J=3 edges, deduct the numberfetched as input message for that edge. This way one gets J=3 partialsums, these are the J=3 outputs, that are sent to the parity checknodes. Send the J=3 outputs back to the corresponding output paritycheck nodes: For each of the J=3 edges of the left node that is beingconsidered, check whether the absolute value of the output message isless than M. If so, MM is replace by M, and M is replaced by thepertaining output message of the codeword bit node, and replace theindex I by the constant label of that edge. Otherwise, check whether theabsolute value of the output is less than the second to minimum MM. Ifso, replace MM by the absolute value of the output message of thecodeword bit node. Replace the T bit with an exclusive OR of the T bitand the hard decision bits of the pertaining output message.

“NEXT CODEWORD BIT NODE”

Exchange input and output parity check node memory section. Do the nextiteration.

“NEXT ITERATION”

Ready, when some stop condition is met. Examples of a stop condition canbe e.g. to include a cyclic redundancy check CRC on the message orcodeword, and stop if the CRC checks positive, or stop if none of thedecoded symbols which are then computed every iteration haven't changedwith respect to the previous iteration.

The message passing decoding method described above can be implementedin a receiver, e.g. an optical reader, using a computer program to carryout the decoding method.

FIG. 3 illustrates an example of an optical system in accordance of theinvention. It comprises a data source and a receiver. The data source isa storage medium 31, e.g. an optical disk, wherein digital encoded dataare stored. The receiver is an optical reader for reading and decodingthe encoded data stored on the optical disk. The reader comprises adecoder 33, for implementing the decoding method as described withreference to FIG. 1 or FIG. 2, and optical reading means 34 to read theencoded data before decoding. The decoded data are then directed to anoutput 35 of the receiver for being treated.

The invention also applies in the case the codeword symbols arenon-binary, but e.g. integers modulo q, q>2, or more generally elementsof a mathematical object called a ring, or elements of a Galois Field.

The LDPC decoder can also be part of a Turbo demodulation scheme, inwhich there is no simple concatenation of a bit-detector and an LDPCdecoder, but iterations of the bit-detector and iterations of the LDPCtype are mixed in one big loop

The drawings and their description herein before illustrate rather thanlimit the invention. It will be evident that there are numerousalternatives, which fall within the scope of the appended claims. Inthis respect, the following closing remarks are made.

There are numerous ways of implementing functions by means of items ofhardware or software, or both. In this respect, the drawings are verydiagrammatic, each representing only one possible embodiment of theinvention. Thus, although a drawing shows different functions asdifferent blocks, this by no means excludes that a single item ofhardware or software carries out several functions. Nor does it excludethat an assembly of items of hardware or software, or both carries out afunction.

CITED REFERENCES, THE DESCRIPTIONS IN [2], [3] AND [4] BEING HEREININCORPORATED BY REFERENCE

-   [1] Marc P. C. Fossorier, “Reduced Complexity Iterative Decoding of    Low-Density Parity Check Codes Based on Belief Propagation”    published in IEEE Transactions on Communications, vol. 47, No. 5,    May 1999-   [2] R. G. Gallager, “Low density parity check codes,” IRE    Transactions on Information Theory IT-8, pp. 21-28, 1962-   [3] F. R. Kschischang, B. J. Frey, H. A. Loeliger, “Factor Graphs    and the Sum-Product Algorithm,” IEEE Trans. on Information Theory,    Volume IT-47, No. 2, February 2001-   [4] J. Hagenauer, E. Offer, L. Papke, “Iterative decoding of binary    block and convolutional codes Information Theory,” IEEE Trans. on    Information Th., Vol. 42 Nr. 2, pp. 429-445, March 1996

1. A decoding method for delivering soft-decision outputs from codewordsymbols encoded with a Low-Density Parity Check code, said codecomprising a number of codeword symbols checked by a number of paritycheck equations, wherein each parity check equation checks a limitednumber of codeword symbols and each codeword symbol is checked by alimited number of parity check equations, the method comprising a step,denoted running minimum step, of determining a minimum value from aninput sequence of input reliability values associated with a set ofcodeword symbols checked by a same parity check equation, wherein saidrunning minimum step comprises the following iterative sub-steps:reading a reliability value from the input sequence of input reliabilityvalues, comparing said reliability value with a stored value,overwriting the stored value with said reliability value if saidreliability value is smaller than said stored value.
 2. A decodingmethod for delivering soft-decision outputs from codeword symbolsencoded with a Low-Density Parity Check code, said code comprising anumber of codeword symbols checked by a number of parity checkequations, wherein each parity check equation checks a limited number ofcodeword symbols and each codeword symbol is checked by a limited numberof parity check equations, the method comprising a step, denoted runningminimum step, of determining minimum values from an input sequence ofinput reliability values associated with a set of codeword symbolschecked by a same parity check equation, wherein said running minimumstep comprises the following iterative sub-steps: reading a reliabilityvalue from the input sequence of input reliability values, comparingsaid reliability value with a first and second stored value, overwritingthe first stored value with said reliability value if said reliabilityvalue is smaller than said first and second stored value, overwritingthe second stored value with said reliability value if said reliabilityvalue is smaller than said second stored value and bigger than saidfirst stored value.
 3. A decoding method as claimed in claim 1, whereinsaid step of determining a minimum value includes a preliminary step ofstoring at least a reference value.
 4. A decoding method as claimed inclaim 1, wherein said input sequence of input reliability values isproduced from said codeword symbols received from a transmission channelor a recording channel.
 5. A decoding method as claimed in claim 4,wherein said input reliability values are derived from the absolutevalues of Log Likelihood Ratios of the codeword symbols received fromthe channel.
 6. A decoding method as claimed in claim 1, wherein themethod comprises a step of computing, for each parity check equation, anoutput sequence of output reliabilities from said input sequence ofinput reliabilities, each output reliability of the output sequencebeing equal to the minimum value of all input reliabilities except theone with the same index in the input sequence, said minimum value beingdetermined with said running minimum step.
 7. A receiver for receivingfrom a channel medium codeword symbols encoded with a Low-Density ParityCheck code, the receiver comprising a decoder for carrying out themethod as claimed in any of claims 1 to
 6. 8. A receiver as claimed inclaim 7, for use in a recording system.
 9. Storage medium for storingcodeword symbols to be processed in accordance with the method asclaimed in any of claims 1 to
 6. 10. A system comprising a source fordelivering codeword symbols encoded with a Low-Density Parity Check codethrough a channel medium and a receiver for receiving said codewordsymbols from the channel medium, wherein said receiver is as claimed inclaim
 7. 11. A computer program product for a receiver computing a setof instructions which when loaded into the receiver causes the receiverto carry out the method as claimed in any of claims 1 to
 6. 12. A signalfor carrying a computer program, the computer program being arranged tocarry out the method as claimed in any of claims 1 to
 6. 13. Makingavailable for downloading the computer program as claimed in claim 11.